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68 lines
1.8 KiB
68 lines
1.8 KiB
5 years ago
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//=========================================================
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// Simulation setup file for esc07_demo project
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//=========================================================
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__var _timer0_interrupt_ID;
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irqBreak()
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{
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__var __AIC_SMR;
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__var __AIC_IECR;
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__var __AIC_IVR;
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// read AIC_IECR instead, since not fully supported by simulator
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__AIC_IECR = __readMemory32(0xFFFFF120, "Memory");
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if(__AIC_IECR & 0x1000)
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{
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__AIC_SMR = __readMemory32(0xFFFFF060, "Memory");
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__AIC_IVR = __readMemory32(0xFFFFF0B0, "Memory"); //AIC_IVR = AIC_SVR[x]
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__writeMemory32(__AIC_IVR, 0xFFFFF100, "Memory"); //AIC_IVR
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__writeMemory32(0x1000, 0xFFFFF10C, "Memory"); //AIC_IPR
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__writeMemory32(0x2, 0xFFFFF114, "Memory"); //AIC_CISR
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}
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return 0;
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}
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setupProcessorRegisters()
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{
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// Write TC0_SR.CPCS with correct status for ISR (Clock enabled; RC Compare Flag = TRUE)
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__writeMemory32(0x00010010, 0xfffa0020, "Memory");
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// Set TX ready flag in USART0 status register
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// USART0_BASE->US_CSR = AT91C_US_TXRDY
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__writeMemory32(0x00000002, 0xfffc0014, "Memory");
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}
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configureTimer0Interrupt()
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{
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__var _master_clock_frequency;
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__var _timer0_period_cycles;
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// Calculate timer0 frequency in master clock cycles
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_master_clock_frequency = 48054857;
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_timer0_period_cycles = _master_clock_frequency / 100;
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if((_master_clock_frequency % 100) >= 50)
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{
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_timer0_period_cycles++;
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}
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__cancelAllInterrupts();
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__enableInterrupts();
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_timer0_interrupt_ID = __orderInterrupt("IRQ", _timer0_period_cycles, _timer0_period_cycles, 0, 0, 0, 100);
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if(-1 == _timer0_interrupt_ID)
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{
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__message "ERROR: failed to order timer 0 interrupt";
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}
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__setCodeBreak("0x18", 0, "irqBreak()", "TRUE", "");
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}
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execUserReset()
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{
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setupProcessorRegisters();
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configureTimer0Interrupt();
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}
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