commit 0ab6862e37ec666bdad58a9604c910248949e3fa Author: Apostolof Date: Thu Apr 22 07:26:34 2021 -0700 Init, Add workshop-1 diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..91fb901 --- /dev/null +++ b/.gitignore @@ -0,0 +1,73 @@ +# User-specific uVision files +*.opt +*.uvopt +*.uvoptx +*.uvgui +*.uvgui.* +*.uvguix.* + +# Listing files +*.cod +*.htm +*.i +*.lst +*.map +*.m51 +*.m66 +# define exception below if needed +*.scr + +# Object and HEX files +*.axf +*.b[0-3][0-9] +*.hex +*.d +*.crf +*.elf +*.hex +*.h86 +*.lib +*.obj +*.o +*.sbr + +# Build files +# define exception below if needed +*.bat +*._ia +*.__i +*._ii + +# Generated output files +/Listings/* +/Objects/* + +# Debugger files +# define exception below if needed +*.ini + +# Other files +*.build_log.htm +*.cdb +*.dep +*.ic +*.lin +*.lnp +*.orc +# define exception below if needed +*.pack +# define exception below if needed +*.pdsc +*.plg +# define exception below if needed +*.sct +*.sfd +*.sfr + +# Miscellaneous +*.tra +*.bin +*.fed +*.l1p +*.l2p +*.iex diff --git a/microprocessors-and-peripherals.uvmpw b/microprocessors-and-peripherals.uvmpw new file mode 100644 index 0000000..22a7e11 --- /dev/null +++ b/microprocessors-and-peripherals.uvmpw @@ -0,0 +1,16 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + WorkSpace + + + .\workshop-1\hash.uvprojx + 1 + 1 + + + diff --git a/workshop-1/DebugConfig/Target_1_STM32F401RETx.dbgconf b/workshop-1/DebugConfig/Target_1_STM32F401RETx.dbgconf new file mode 100644 index 0000000..27812f3 --- /dev/null +++ b/workshop-1/DebugConfig/Target_1_STM32F401RETx.dbgconf @@ -0,0 +1,41 @@ +// File: STM32F401xBCDE_411xCE.dbgconf +// Version: 1.0.0 +// Note: refer to STM32F401xB/C STM32F401xD/E reference manual (RM0368) +// refer to STM32F401xB/C STM32F401xD/E datasheet +// refer to STM32F411xC/E reference manual (RM0383) +// refer to STM32F411xC/E datasheet + +// <<< Use Configuration Wizard in Context Menu >>> + +// Debug MCU configuration register (DBGMCU_CR) +// DBG_STANDBY Debug Standby Mode +// DBG_STOP Debug Stop Mode +// DBG_SLEEP Debug Sleep Mode +// +DbgMCU_CR = 0x00000007; + +// Debug MCU APB1 freeze register (DBGMCU_APB1_FZ) +// Reserved bits must be kept at reset value +// DBG_I2C3_SMBUS_TIMEOUT I2C3 SMBUS timeout mode stopped when core is halted +// DBG_I2C2_SMBUS_TIMEOUT I2C2 SMBUS timeout mode stopped when core is halted +// DBG_I2C1_SMBUS_TIMEOUT I2C1 SMBUS timeout mode stopped when core is halted +// DBG_IWDG_STOP Independent watchdog stopped when core is halted +// DBG_WWDG_STOP Window watchdog stopped when core is halted +// DBG_RTC_STOP RTC stopped when core is halted +// DBG_TIM5_STOP TIM5 counter stopped when core is halted +// DBG_TIM4_STOP TIM4 counter stopped when core is halted +// DBG_TIM3_STOP TIM3 counter stopped when core is halted +// DBG_TIM2_STOP TIM2 counter stopped when core is halted +// +DbgMCU_APB1_Fz = 0x00000000; + +// Debug MCU APB2 freeze register (DBGMCU_APB2_FZ) +// Reserved bits must be kept at reset value +// DBG_TIM11_STOP TIM11 counter stopped when core is halted +// DBG_TIM10_STOP TIM10 counter stopped when core is halted +// DBG_TIM9_STOP TIM9 counter stopped when core is halted +// DBG_TIM1_STOP TIM1 counter stopped when core is halted +// +DbgMCU_APB2_Fz = 0x00000000; + +// <<< end of configuration section >>> \ No newline at end of file diff --git a/workshop-1/EventRecorderStub.scvd b/workshop-1/EventRecorderStub.scvd new file mode 100644 index 0000000..0fb3ee5 --- /dev/null +++ b/workshop-1/EventRecorderStub.scvd @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/workshop-1/Listings/hash_function.txt b/workshop-1/Listings/hash_function.txt new file mode 100644 index 0000000..92372bc --- /dev/null +++ b/workshop-1/Listings/hash_function.txt @@ -0,0 +1,119 @@ +; generated by Component: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] +; commandline ArmCC [--list --split_sections --debug -c --asm --interleave -o.\objects\hash_function.o --asm_dir=.\Listings\ --list_dir=.\Listings\ --depend=.\objects\hash_function.d --cpu=Cortex-M4.fp.sp --apcs=interwork -O0 --diag_suppress=9931 -I.\RTE\_Target_1 -IC:\Users\User\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include -IC:\Users\User\AppData\Local\Arm\Packs\Keil\STM32F4xx_DFP\2.15.0\Drivers\CMSIS\Device\ST\STM32F4xx\Include -D__UVISION_VERSION=534 -D_RTE_ -DSTM32F401xE -D_RTE_ --omf_browse=.\objects\hash_function.crf hash_function.c] + THUMB + + AREA ||i.main||, CODE, READONLY, ALIGN=2 + + REQUIRE _printf_percent + REQUIRE _printf_d + REQUIRE _printf_int_dec + main PROC +;;;45 +;;;46 int main(void) +000000 b510 PUSH {r4,lr} +;;;47 { +;;;48 static char STRING_TO_HASH[] = "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789!!@#$%*&"; +;;;49 int hash = 0; +000002 2400 MOVS r4,#0 +;;;50 +;;;51 hash = generate_hash(STRING_TO_HASH, hashtbl); +000004 4905 LDR r1,|L1.28| +000006 4806 LDR r0,|L1.32| +000008 f7fffffe BL generate_hash +00000c 4604 MOV r4,r0 +;;;52 printf("%d", hash); +00000e 4621 MOV r1,r4 +000010 a004 ADR r0,|L1.36| +000012 f7fffffe BL __2printf +;;;53 +;;;54 return 0; +000016 2000 MOVS r0,#0 +;;;55 } +000018 bd10 POP {r4,pc} + ENDP + +00001a 0000 DCW 0x0000 + |L1.28| + DCD |symbol_number.8| + |L1.32| + DCD STRING_TO_HASH + |L1.36| +000024 256400 DCB "%d",0 +000027 00 DCB 0 + + AREA ||.constdata||, DATA, READONLY, ALIGN=0 + + |symbol_number.8| +000000 120b0a15 DCB 0x12,0x0b,0x0a,0x15 +000004 07050916 DCB 0x07,0x05,0x09,0x16 +000008 11020c03 DCB 0x11,0x02,0x0c,0x03 +00000c 13010e10 DCB 0x13,0x01,0x0e,0x10 +000010 14081704 DCB 0x14,0x08,0x17,0x04 +000014 1a0f0618 DCB 0x1a,0x0f,0x06,0x18 +000018 0d19 DCB 0x0d,0x19 + + AREA ||.data||, DATA, ALIGN=0 + + STRING_TO_HASH +000000 41424344 DCB 0x41,0x42,0x43,0x44 +000004 45464748 DCB 0x45,0x46,0x47,0x48 +000008 494a4b4c DCB 0x49,0x4a,0x4b,0x4c +00000c 4d4e4f50 DCB 0x4d,0x4e,0x4f,0x50 +000010 51525354 DCB 0x51,0x52,0x53,0x54 +000014 55565758 DCB 0x55,0x56,0x57,0x58 +000018 595a3031 DCB 0x59,0x5a,0x30,0x31 +00001c 32333435 DCB 0x32,0x33,0x34,0x35 +000020 36373839 DCB 0x36,0x37,0x38,0x39 +000024 21214023 DCB 0x21,0x21,0x40,0x23 +000028 24252a26 DCB 0x24,0x25,0x2a,0x26 +00002c 00 DCB 0x00 + +;*** Start embedded assembler *** + +#line 1 "hash_function.c" + AREA ||.emb_text||, CODE + THUMB + EXPORT |generate_hash| +#line 8 +|generate_hash| PROC +#line 9 + + +input_str RN r0 +hashtbl RN r1 +curr_char RN r2 +hash_val RN r3 + + MOV hash_val, #0 +hash_loop + LDRB curr_char, [input_str] + CMP curr_char, #48 + BLS hash_skip + + CMP curr_char, #57 + SUBLS hash_val, curr_char + ADDLS hash_val, #48 + BLS hash_skip + + CMP curr_char, #65 - 1 + BLS hash_skip + + CMP curr_char, #90 + BHI hash_skip + + SUB r4, curr_char, #65 + ADD r4, hashtbl, r4 + LDRB r5, [r4] + ADD hash_val, r5 + +hash_skip + ADDS input_str, input_str, #1 + CMP curr_char, #0 + BNE hash_loop + MOVEQ r0, hash_val + BX lr + ENDP + +;*** End embedded assembler *** + + __ARM_use_no_argv EQU 0 diff --git a/workshop-1/Listings/retarget_io.txt b/workshop-1/Listings/retarget_io.txt new file mode 100644 index 0000000..8af3bd2 --- /dev/null +++ b/workshop-1/Listings/retarget_io.txt @@ -0,0 +1,608 @@ +; generated by Component: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] +; commandline ArmCC [--list --split_sections --debug -c --asm --interleave -o.\objects\retarget_io.o --asm_dir=.\Listings\ --list_dir=.\Listings\ --depend=.\objects\retarget_io.d --cpu=Cortex-M4.fp.sp --apcs=interwork -O0 --diag_suppress=9931 -I.\RTE\_Target_1 -IC:\Users\User\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include -IC:\Users\User\AppData\Local\Arm\Packs\Keil\STM32F4xx_DFP\2.15.0\Drivers\CMSIS\Device\ST\STM32F4xx\Include -D__UVISION_VERSION=534 -D_RTE_ -DSTM32F401xE -D_RTE_ --omf_browse=.\objects\retarget_io.crf C:\Users\User\AppData\Local\Arm\Packs\Keil\ARM_Compiler\1.6.3\Source\retarget_io.c] + THUMB + + AREA ||i.ITM_ReceiveChar||, CODE, READONLY, ALIGN=2 + + ITM_ReceiveChar PROC +;;;113 int32_t ITM_ReceiveChar (void); +;;;114 int32_t ITM_ReceiveChar (void) { +000000 f04f30ff MOV r0,#0xffffffff +;;;115 int32_t ch = -1; /* no character available */ +;;;116 +;;;117 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { +000004 4905 LDR r1,|L1.28| +000006 6809 LDR r1,[r1,#0] ; ITM_RxBuffer +000008 4a05 LDR r2,|L1.32| +00000a 4291 CMP r1,r2 +00000c d004 BEQ |L1.24| +;;;118 ch = ITM_RxBuffer; +00000e 4903 LDR r1,|L1.28| +000010 6808 LDR r0,[r1,#0] ; ITM_RxBuffer +;;;119 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ +000012 4611 MOV r1,r2 +000014 4a01 LDR r2,|L1.28| +000016 6011 STR r1,[r2,#0] ; ITM_RxBuffer + |L1.24| +;;;120 } +;;;121 +;;;122 return (ch); +;;;123 } +000018 4770 BX lr +;;;124 + ENDP + +00001a 0000 DCW 0x0000 + |L1.28| + DCD ITM_RxBuffer + |L1.32| + DCD 0x5aa55aa5 + + AREA ||i.ITM_SendChar||, CODE, READONLY, ALIGN=2 + + ITM_SendChar PROC +;;;95 int32_t ITM_SendChar (int32_t ch); +;;;96 int32_t ITM_SendChar (int32_t ch) { +000000 490a LDR r1,|L2.44| +;;;97 if ((ITM_TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ +000002 6809 LDR r1,[r1,#0] +000004 f0010101 AND r1,r1,#1 +000008 b171 CBZ r1,|L2.40| +;;;98 (ITM_TER & (1UL << 0) )) { /* ITM Port #0 enabled */ +00000a 4908 LDR r1,|L2.44| +00000c 3980 SUBS r1,r1,#0x80 +00000e 6809 LDR r1,[r1,#0] +000010 f0010101 AND r1,r1,#1 +000014 b141 CBZ r1,|L2.40| +;;;99 while (ITM_PORT0_U32 == 0); +000016 bf00 NOP + |L2.24| +000018 f04f4160 MOV r1,#0xe0000000 +00001c 6809 LDR r1,[r1,#0] +00001e 2900 CMP r1,#0 +000020 d0fa BEQ |L2.24| +;;;100 ITM_PORT0_U8 = (uint8_t)ch; +000022 f04f4260 MOV r2,#0xe0000000 +000026 7010 STRB r0,[r2,#0] + |L2.40| +;;;101 } +;;;102 return (ch); +;;;103 } +000028 4770 BX lr +;;;104 + ENDP + +00002a 0000 DCW 0x0000 + |L2.44| + DCD 0xe0000e80 + + AREA ||i._sys_close||, CODE, READONLY, ALIGN=1 + + _sys_close PROC +;;;458 __attribute__((weak)) +;;;459 int _sys_close (FILEHANDLE fh) { +000000 4601 MOV r1,r0 +;;;460 +;;;461 switch (fh) { +000002 f46f4000 MVN r0,#0x8000 +000006 4408 ADD r0,r0,r1 +000008 b120 CBZ r0,|L3.20| +00000a 2801 CMP r0,#1 +00000c d004 BEQ |L3.24| +00000e 2802 CMP r0,#2 +000010 d106 BNE |L3.32| +000012 e003 B |L3.28| + |L3.20| +;;;462 case FH_STDIN: +;;;463 return (0); +000014 2000 MOVS r0,#0 + |L3.22| +;;;464 case FH_STDOUT: +;;;465 return (0); +;;;466 case FH_STDERR: +;;;467 return (0); +;;;468 } +;;;469 +;;;470 #ifdef RTE_Compiler_IO_File +;;;471 #ifdef RTE_Compiler_IO_File_FS +;;;472 return (__sys_close(fh)); +;;;473 #endif +;;;474 #else +;;;475 return (-1); +;;;476 #endif +;;;477 } +000016 4770 BX lr + |L3.24| +000018 2000 MOVS r0,#0 ;465 +00001a e7fc B |L3.22| + |L3.28| +00001c 2000 MOVS r0,#0 ;467 +00001e e7fa B |L3.22| + |L3.32| +000020 f04f30ff MOV r0,#0xffffffff ;475 +000024 e7f7 B |L3.22| +;;;478 #endif + ENDP + + + AREA ||i._sys_flen||, CODE, READONLY, ALIGN=1 + + _sys_flen PROC +;;;743 __attribute__((weak)) +;;;744 long _sys_flen (FILEHANDLE fh) { +000000 4601 MOV r1,r0 +;;;745 +;;;746 switch (fh) { +000002 f46f4000 MVN r0,#0x8000 +000006 4408 ADD r0,r0,r1 +000008 b120 CBZ r0,|L4.20| +00000a 2801 CMP r0,#1 +00000c d004 BEQ |L4.24| +00000e 2802 CMP r0,#2 +000010 d106 BNE |L4.32| +000012 e003 B |L4.28| + |L4.20| +;;;747 case FH_STDIN: +;;;748 return (0); +000014 2000 MOVS r0,#0 + |L4.22| +;;;749 case FH_STDOUT: +;;;750 return (0); +;;;751 case FH_STDERR: +;;;752 return (0); +;;;753 } +;;;754 +;;;755 #ifdef RTE_Compiler_IO_File +;;;756 #ifdef RTE_Compiler_IO_File_FS +;;;757 return (__sys_flen(fh)); +;;;758 #endif +;;;759 #else +;;;760 return (0); +;;;761 #endif +;;;762 } +000016 4770 BX lr + |L4.24| +000018 2000 MOVS r0,#0 ;750 +00001a e7fc B |L4.22| + |L4.28| +00001c 2000 MOVS r0,#0 ;752 +00001e e7fa B |L4.22| + |L4.32| +000020 2000 MOVS r0,#0 ;760 +000022 e7f8 B |L4.22| +;;;763 #endif + ENDP + + + AREA ||i._sys_istty||, CODE, READONLY, ALIGN=1 + + _sys_istty PROC +;;;669 __attribute__((weak)) +;;;670 int _sys_istty (FILEHANDLE fh) { +000000 4601 MOV r1,r0 +;;;671 +;;;672 switch (fh) { +000002 f46f4000 MVN r0,#0x8000 +000006 4408 ADD r0,r0,r1 +000008 b120 CBZ r0,|L5.20| +00000a 2801 CMP r0,#1 +00000c d004 BEQ |L5.24| +00000e 2802 CMP r0,#2 +000010 d106 BNE |L5.32| +000012 e003 B |L5.28| + |L5.20| +;;;673 case FH_STDIN: +;;;674 return (1); +000014 2001 MOVS r0,#1 + |L5.22| +;;;675 case FH_STDOUT: +;;;676 return (1); +;;;677 case FH_STDERR: +;;;678 return (1); +;;;679 } +;;;680 +;;;681 return (0); +;;;682 } +000016 4770 BX lr + |L5.24| +000018 2001 MOVS r0,#1 ;676 +00001a e7fc B |L5.22| + |L5.28| +00001c 2001 MOVS r0,#1 ;678 +00001e e7fa B |L5.22| + |L5.32| +000020 2000 MOVS r0,#0 ;681 +000022 e7f8 B |L5.22| +;;;683 #endif + ENDP + + + AREA ||i._sys_open||, CODE, READONLY, ALIGN=2 + + _sys_open PROC +;;;412 __attribute__((weak)) +;;;413 FILEHANDLE _sys_open (const char *name, int openmode) { +000000 b570 PUSH {r4-r6,lr} +000002 4604 MOV r4,r0 +000004 460d MOV r5,r1 +;;;414 #if (!defined(RTE_Compiler_IO_File)) +;;;415 (void)openmode; +;;;416 #endif +;;;417 +;;;418 if (name == NULL) { +000006 b914 CBNZ r4,|L6.14| +;;;419 return (-1); +000008 f04f30ff MOV r0,#0xffffffff + |L6.12| +;;;420 } +;;;421 +;;;422 if (name[0] == ':') { +;;;423 if (strcmp(name, ":STDIN") == 0) { +;;;424 return (FH_STDIN); +;;;425 } +;;;426 if (strcmp(name, ":STDOUT") == 0) { +;;;427 return (FH_STDOUT); +;;;428 } +;;;429 if (strcmp(name, ":STDERR") == 0) { +;;;430 return (FH_STDERR); +;;;431 } +;;;432 return (-1); +;;;433 } +;;;434 +;;;435 #ifdef RTE_Compiler_IO_File +;;;436 #ifdef RTE_Compiler_IO_File_FS +;;;437 return (__sys_open(name, openmode)); +;;;438 #endif +;;;439 #else +;;;440 return (-1); +;;;441 #endif +;;;442 } +00000c bd70 POP {r4-r6,pc} + |L6.14| +00000e 7820 LDRB r0,[r4,#0] ;422 +000010 283a CMP r0,#0x3a ;422 +000012 d11a BNE |L6.74| +000014 a10e ADR r1,|L6.80| +000016 4620 MOV r0,r4 ;423 +000018 f7fffffe BL strcmp +00001c b910 CBNZ r0,|L6.36| +00001e f2480001 MOV r0,#0x8001 ;424 +000022 e7f3 B |L6.12| + |L6.36| +000024 a10c ADR r1,|L6.88| +000026 4620 MOV r0,r4 ;426 +000028 f7fffffe BL strcmp +00002c b910 CBNZ r0,|L6.52| +00002e f2480002 MOV r0,#0x8002 ;427 +000032 e7eb B |L6.12| + |L6.52| +000034 a10a ADR r1,|L6.96| +000036 4620 MOV r0,r4 ;429 +000038 f7fffffe BL strcmp +00003c b910 CBNZ r0,|L6.68| +00003e f2480003 MOV r0,#0x8003 ;430 +000042 e7e3 B |L6.12| + |L6.68| +000044 f04f30ff MOV r0,#0xffffffff ;432 +000048 e7e0 B |L6.12| + |L6.74| +00004a f04f30ff MOV r0,#0xffffffff ;440 +00004e e7dd B |L6.12| +;;;443 #endif + ENDP + + |L6.80| +000050 3a535444 DCB ":STDIN",0 +000054 494e00 +000057 00 DCB 0 + |L6.88| +000058 3a535444 DCB ":STDOUT",0 +00005c 4f555400 + |L6.96| +000060 3a535444 DCB ":STDERR",0 +000064 45525200 + + AREA ||i._sys_read||, CODE, READONLY, ALIGN=1 + + _sys_read PROC +;;;576 __attribute__((weak)) +;;;577 int _sys_read (FILEHANDLE fh, uint8_t *buf, uint32_t len, int mode) { +000000 e92d41f0 PUSH {r4-r8,lr} +000004 4607 MOV r7,r0 +000006 460e MOV r6,r1 +000008 4614 MOV r4,r2 +00000a 4698 MOV r8,r3 +;;;578 #ifdef RTE_Compiler_IO_STDIN +;;;579 int ch; +;;;580 #elif (!defined(RTE_Compiler_IO_File)) +;;;581 (void)buf; +;;;582 (void)len; +;;;583 #endif +;;;584 (void)mode; +;;;585 +;;;586 switch (fh) { +00000c f46f4000 MVN r0,#0x8000 +000010 4438 ADD r0,r0,r7 +000012 b120 CBZ r0,|L7.30| +000014 2801 CMP r0,#1 +000016 d010 BEQ |L7.58| +000018 2802 CMP r0,#2 +00001a d114 BNE |L7.70| +00001c e010 B |L7.64| + |L7.30| +;;;587 case FH_STDIN: +;;;588 #ifdef RTE_Compiler_IO_STDIN +;;;589 ch = stdin_getchar(); +00001e f7fffffe BL stdin_getchar +000022 4605 MOV r5,r0 +;;;590 if (ch < 0) { +000024 2d00 CMP r5,#0 +000026 da03 BGE |L7.48| +;;;591 return ((int)(len | 0x80000000U)); +000028 f0444000 ORR r0,r4,#0x80000000 + |L7.44| +;;;592 } +;;;593 *buf++ = (uint8_t)ch; +;;;594 #if (STDIN_ECHO != 0) +;;;595 stdout_putchar(ch); +;;;596 #endif +;;;597 len--; +;;;598 return ((int)(len)); +;;;599 #else +;;;600 return ((int)(len | 0x80000000U)); +;;;601 #endif +;;;602 case FH_STDOUT: +;;;603 return (-1); +;;;604 case FH_STDERR: +;;;605 return (-1); +;;;606 } +;;;607 +;;;608 #ifdef RTE_Compiler_IO_File +;;;609 #ifdef RTE_Compiler_IO_File_FS +;;;610 return (__sys_read(fh, buf, len)); +;;;611 #endif +;;;612 #else +;;;613 return (-1); +;;;614 #endif +;;;615 } +00002c e8bd81f0 POP {r4-r8,pc} + |L7.48| +000030 f8065b01 STRB r5,[r6],#1 ;593 +000034 1e64 SUBS r4,r4,#1 ;597 +000036 4620 MOV r0,r4 ;598 +000038 e7f8 B |L7.44| + |L7.58| +00003a f04f30ff MOV r0,#0xffffffff ;603 +00003e e7f5 B |L7.44| + |L7.64| +000040 f04f30ff MOV r0,#0xffffffff ;605 +000044 e7f2 B |L7.44| + |L7.70| +000046 f04f30ff MOV r0,#0xffffffff ;613 +00004a e7ef B |L7.44| +;;;616 #endif + ENDP + + + AREA ||i._sys_seek||, CODE, READONLY, ALIGN=1 + + _sys_seek PROC +;;;701 __attribute__((weak)) +;;;702 int _sys_seek (FILEHANDLE fh, long pos) { +000000 4602 MOV r2,r0 +;;;703 #if (!defined(RTE_Compiler_IO_File)) +;;;704 (void)pos; +;;;705 #endif +;;;706 +;;;707 switch (fh) { +000002 f46f4000 MVN r0,#0x8000 +000006 4410 ADD r0,r0,r2 +000008 b120 CBZ r0,|L8.20| +00000a 2801 CMP r0,#1 +00000c d005 BEQ |L8.26| +00000e 2802 CMP r0,#2 +000010 d109 BNE |L8.38| +000012 e005 B |L8.32| + |L8.20| +;;;708 case FH_STDIN: +;;;709 return (-1); +000014 f04f30ff MOV r0,#0xffffffff + |L8.24| +;;;710 case FH_STDOUT: +;;;711 return (-1); +;;;712 case FH_STDERR: +;;;713 return (-1); +;;;714 } +;;;715 +;;;716 #ifdef RTE_Compiler_IO_File +;;;717 #ifdef RTE_Compiler_IO_File_FS +;;;718 return (__sys_seek(fh, (uint32_t)pos)); +;;;719 #endif +;;;720 #else +;;;721 return (-1); +;;;722 #endif +;;;723 } +000018 4770 BX lr + |L8.26| +00001a f04f30ff MOV r0,#0xffffffff ;711 +00001e e7fb B |L8.24| + |L8.32| +000020 f04f30ff MOV r0,#0xffffffff ;713 +000024 e7f8 B |L8.24| + |L8.38| +000026 f04f30ff MOV r0,#0xffffffff ;721 +00002a e7f5 B |L8.24| +;;;724 #endif + ENDP + + + AREA ||i._sys_write||, CODE, READONLY, ALIGN=1 + + _sys_write PROC +;;;500 __attribute__((weak)) +;;;501 int _sys_write (FILEHANDLE fh, const uint8_t *buf, uint32_t len, int mode) { +000000 e92d41f0 PUSH {r4-r8,lr} +000004 4607 MOV r7,r0 +000006 460c MOV r4,r1 +000008 4615 MOV r5,r2 +00000a 4698 MOV r8,r3 +;;;502 #if (defined(RTE_Compiler_IO_STDOUT) || defined(RTE_Compiler_IO_STDERR)) +;;;503 int ch; +;;;504 #elif (!defined(RTE_Compiler_IO_File)) +;;;505 (void)buf; +;;;506 (void)len; +;;;507 #endif +;;;508 (void)mode; +;;;509 +;;;510 switch (fh) { +00000c f46f4000 MVN r0,#0x8000 +000010 4438 ADD r0,r0,r7 +000012 b120 CBZ r0,|L9.30| +000014 2801 CMP r0,#1 +000016 d006 BEQ |L9.38| +000018 2802 CMP r0,#2 +00001a d11a BNE |L9.82| +00001c e00e B |L9.60| + |L9.30| +;;;511 case FH_STDIN: +;;;512 return (-1); +00001e f04f30ff MOV r0,#0xffffffff + |L9.34| +;;;513 case FH_STDOUT: +;;;514 #ifdef RTE_Compiler_IO_STDOUT +;;;515 for (; len; len--) { +;;;516 ch = *buf++; +;;;517 #if (STDOUT_CR_LF != 0) +;;;518 if (ch == '\n') stdout_putchar('\r'); +;;;519 #endif +;;;520 stdout_putchar(ch); +;;;521 } +;;;522 #endif +;;;523 return (0); +;;;524 case FH_STDERR: +;;;525 #ifdef RTE_Compiler_IO_STDERR +;;;526 for (; len; len--) { +;;;527 ch = *buf++; +;;;528 #if (STDERR_CR_LF != 0) +;;;529 if (ch == '\n') stderr_putchar('\r'); +;;;530 #endif +;;;531 stderr_putchar(ch); +;;;532 } +;;;533 #endif +;;;534 return (0); +;;;535 } +;;;536 +;;;537 #ifdef RTE_Compiler_IO_File +;;;538 #ifdef RTE_Compiler_IO_File_FS +;;;539 return (__sys_write(fh, buf, len)); +;;;540 #endif +;;;541 #else +;;;542 return (-1); +;;;543 #endif +;;;544 } +000022 e8bd81f0 POP {r4-r8,pc} + |L9.38| +000026 e005 B |L9.52| + |L9.40| +000028 f8146b01 LDRB r6,[r4],#1 ;516 +00002c 4630 MOV r0,r6 ;520 +00002e f7fffffe BL stdout_putchar +000032 1e6d SUBS r5,r5,#1 ;515 + |L9.52| +000034 2d00 CMP r5,#0 ;515 +000036 d1f7 BNE |L9.40| +000038 2000 MOVS r0,#0 ;523 +00003a e7f2 B |L9.34| + |L9.60| +00003c e005 B |L9.74| + |L9.62| +00003e f8146b01 LDRB r6,[r4],#1 ;527 +000042 4630 MOV r0,r6 ;531 +000044 f7fffffe BL stderr_putchar +000048 1e6d SUBS r5,r5,#1 ;526 + |L9.74| +00004a 2d00 CMP r5,#0 ;526 +00004c d1f7 BNE |L9.62| +00004e 2000 MOVS r0,#0 ;534 +000050 e7e7 B |L9.34| + |L9.82| +000052 f04f30ff MOV r0,#0xffffffff ;542 +000056 e7e4 B |L9.34| +;;;545 #endif + ENDP + + + AREA ||i.stderr_putchar||, CODE, READONLY, ALIGN=1 + + stderr_putchar PROC +;;;202 #elif defined(RTE_Compiler_IO_STDERR_ITM) +;;;203 static int stderr_putchar (int ch) { +000000 b500 PUSH {lr} +000002 4603 MOV r3,r0 +;;;204 return (ITM_SendChar(ch)); +000004 4618 MOV r0,r3 +000006 f7fffffe BL ITM_SendChar +;;;205 } +00000a bd00 POP {pc} +;;;206 #elif defined(RTE_Compiler_IO_STDERR_BKPT) + ENDP + + + AREA ||i.stdin_getchar||, CODE, READONLY, ALIGN=1 + + stdin_getchar PROC +;;;136 #elif defined(RTE_Compiler_IO_STDIN_ITM) +;;;137 static int stdin_getchar (void) { +000000 b500 PUSH {lr} +;;;138 int32_t ch; +;;;139 +;;;140 do { +000002 bf00 NOP + |L11.4| +;;;141 ch = ITM_ReceiveChar(); +000004 f7fffffe BL ITM_ReceiveChar +;;;142 } while (ch == -1); +000008 1c41 ADDS r1,r0,#1 +00000a 2900 CMP r1,#0 +00000c d0fa BEQ |L11.4| +;;;143 return (ch); +;;;144 } +00000e bd00 POP {pc} +;;;145 #elif defined(RTE_Compiler_IO_STDIN_BKPT) + ENDP + + + AREA ||i.stdout_putchar||, CODE, READONLY, ALIGN=1 + + stdout_putchar PROC +;;;165 #elif defined(RTE_Compiler_IO_STDOUT_ITM) +;;;166 static int stdout_putchar (int ch) { +000000 b500 PUSH {lr} +000002 4603 MOV r3,r0 +;;;167 return (ITM_SendChar(ch)); +000004 4618 MOV r0,r3 +000006 f7fffffe BL ITM_SendChar +;;;168 } +00000a bd00 POP {pc} +;;;169 #elif defined(RTE_Compiler_IO_STDOUT_EVR) + ENDP + + + AREA ||.constdata||, DATA, READONLY, ALIGN=0 + + __stdin_name +000000 3a535444 DCB 0x3a,0x53,0x54,0x44 +000004 494e00 DCB 0x49,0x4e,0x00 + __stdout_name +000007 3a DCB 0x3a +000008 5354444f DCB 0x53,0x54,0x44,0x4f +00000c 555400 DCB 0x55,0x54,0x00 + __stderr_name +00000f 3a DCB 0x3a +000010 53544445 DCB 0x53,0x54,0x44,0x45 +000014 525200 DCB 0x52,0x52,0x00 + + AREA ||.data||, DATA, ALIGN=2 + + ITM_RxBuffer + DCD 0x5aa55aa5 diff --git a/workshop-1/Listings/system_stm32f4xx.txt b/workshop-1/Listings/system_stm32f4xx.txt new file mode 100644 index 0000000..dbc730d --- /dev/null +++ b/workshop-1/Listings/system_stm32f4xx.txt @@ -0,0 +1,239 @@ +; generated by Component: ARM Compiler 5.06 update 7 (build 960) Tool: ArmCC [4d365d] +; commandline ArmCC [--list --split_sections --debug -c --asm --interleave -o.\objects\system_stm32f4xx.o --asm_dir=.\Listings\ --list_dir=.\Listings\ --depend=.\objects\system_stm32f4xx.d --cpu=Cortex-M4.fp.sp --apcs=interwork -O0 --diag_suppress=9931 -I.\RTE\_Target_1 -IC:\Users\User\AppData\Local\Arm\Packs\ARM\CMSIS\5.7.0\CMSIS\Core\Include -IC:\Users\User\AppData\Local\Arm\Packs\Keil\STM32F4xx_DFP\2.15.0\Drivers\CMSIS\Device\ST\STM32F4xx\Include -D__UVISION_VERSION=534 -D_RTE_ -DSTM32F401xE -D_RTE_ --omf_browse=.\objects\system_stm32f4xx.crf RTE\Device\STM32F401RETx\system_stm32f4xx.c] + THUMB + + AREA ||i.SystemCoreClockUpdate||, CODE, READONLY, ALIGN=2 + + SystemCoreClockUpdate PROC +;;;204 */ +;;;205 void SystemCoreClockUpdate(void) +000000 b570 PUSH {r4-r6,lr} +;;;206 { +;;;207 uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; +000002 2000 MOVS r0,#0 +000004 2200 MOVS r2,#0 +000006 2302 MOVS r3,#2 +000008 2400 MOVS r4,#0 +00000a 2102 MOVS r1,#2 +;;;208 +;;;209 /* Get SYSCLK source -------------------------------------------------------*/ +;;;210 tmp = RCC->CFGR & RCC_CFGR_SWS; +00000c 4d27 LDR r5,|L1.172| +00000e 682d LDR r5,[r5,#0] +000010 f005000c AND r0,r5,#0xc +;;;211 +;;;212 switch (tmp) +000014 b120 CBZ r0,|L1.32| +000016 2804 CMP r0,#4 +000018 d006 BEQ |L1.40| +00001a 2808 CMP r0,#8 +00001c d134 BNE |L1.136| +00001e e007 B |L1.48| + |L1.32| +;;;213 { +;;;214 case 0x00: /* HSI used as system clock source */ +;;;215 SystemCoreClock = HSI_VALUE; +000020 4d23 LDR r5,|L1.176| +000022 4e24 LDR r6,|L1.180| +000024 6035 STR r5,[r6,#0] ; SystemCoreClock +;;;216 break; +000026 e033 B |L1.144| + |L1.40| +;;;217 case 0x04: /* HSE used as system clock source */ +;;;218 SystemCoreClock = HSE_VALUE; +000028 4d23 LDR r5,|L1.184| +00002a 4e22 LDR r6,|L1.180| +00002c 6035 STR r5,[r6,#0] ; SystemCoreClock +;;;219 break; +00002e e02f B |L1.144| + |L1.48| +;;;220 case 0x08: /* PLL used as system clock source */ +;;;221 +;;;222 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N +;;;223 SYSCLK = PLL_VCO / PLL_P +;;;224 */ +;;;225 pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; +000030 4d1e LDR r5,|L1.172| +000032 1f2d SUBS r5,r5,#4 +000034 682d LDR r5,[r5,#0] +000036 f3c55480 UBFX r4,r5,#22,#1 +;;;226 pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; +00003a 4d1c LDR r5,|L1.172| +00003c 1f2d SUBS r5,r5,#4 +00003e 682d LDR r5,[r5,#0] +000040 f005013f AND r1,r5,#0x3f +;;;227 +;;;228 if (pllsource != 0) +000044 b154 CBZ r4,|L1.92| +;;;229 { +;;;230 /* HSE used as PLL clock source */ +;;;231 pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); +000046 4d1c LDR r5,|L1.184| +000048 fbb5f5f1 UDIV r5,r5,r1 +00004c 4e17 LDR r6,|L1.172| +00004e 1f36 SUBS r6,r6,#4 +000050 6836 LDR r6,[r6,#0] +000052 f3c61688 UBFX r6,r6,#6,#9 +000056 fb05f206 MUL r2,r5,r6 +00005a e009 B |L1.112| + |L1.92| +;;;232 } +;;;233 else +;;;234 { +;;;235 /* HSI used as PLL clock source */ +;;;236 pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); +00005c 4d14 LDR r5,|L1.176| +00005e fbb5f5f1 UDIV r5,r5,r1 +000062 4e12 LDR r6,|L1.172| +000064 1f36 SUBS r6,r6,#4 +000066 6836 LDR r6,[r6,#0] +000068 f3c61688 UBFX r6,r6,#6,#9 +00006c fb05f206 MUL r2,r5,r6 + |L1.112| +;;;237 } +;;;238 +;;;239 pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; +000070 4d0e LDR r5,|L1.172| +000072 1f2d SUBS r5,r5,#4 +000074 682d LDR r5,[r5,#0] +000076 f3c54501 UBFX r5,r5,#16,#2 +00007a 1c6d ADDS r5,r5,#1 +00007c 006b LSLS r3,r5,#1 +;;;240 SystemCoreClock = pllvco/pllp; +00007e fbb2f5f3 UDIV r5,r2,r3 +000082 4e0c LDR r6,|L1.180| +000084 6035 STR r5,[r6,#0] ; SystemCoreClock +;;;241 break; +000086 e003 B |L1.144| + |L1.136| +;;;242 default: +;;;243 SystemCoreClock = HSI_VALUE; +000088 4d09 LDR r5,|L1.176| +00008a 4e0a LDR r6,|L1.180| +00008c 6035 STR r5,[r6,#0] ; SystemCoreClock +;;;244 break; +00008e bf00 NOP + |L1.144| +000090 bf00 NOP ;216 +;;;245 } +;;;246 /* Compute HCLK frequency --------------------------------------------------*/ +;;;247 /* Get HCLK prescaler */ +;;;248 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; +000092 4d06 LDR r5,|L1.172| +000094 682d LDR r5,[r5,#0] +000096 f3c51503 UBFX r5,r5,#4,#4 +00009a 4e08 LDR r6,|L1.188| +00009c 5d70 LDRB r0,[r6,r5] +;;;249 /* HCLK frequency */ +;;;250 SystemCoreClock >>= tmp; +00009e 4d05 LDR r5,|L1.180| +0000a0 682d LDR r5,[r5,#0] ; SystemCoreClock +0000a2 40c5 LSRS r5,r5,r0 +0000a4 4e03 LDR r6,|L1.180| +0000a6 6035 STR r5,[r6,#0] ; SystemCoreClock +;;;251 } +0000a8 bd70 POP {r4-r6,pc} +;;;252 + ENDP + +0000aa 0000 DCW 0x0000 + |L1.172| + DCD 0x40023808 + |L1.176| + DCD 0x00f42400 + |L1.180| + DCD SystemCoreClock + |L1.184| + DCD 0x017d7840 + |L1.188| + DCD AHBPrescTable + + AREA ||i.SystemInit||, CODE, READONLY, ALIGN=2 + + SystemInit PROC +;;;149 */ +;;;150 void SystemInit(void) +000000 4805 LDR r0,|L2.24| +;;;151 { +;;;152 /* FPU settings ------------------------------------------------------------*/ +;;;153 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) +;;;154 SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ +000002 6800 LDR r0,[r0,#0] +000004 f4400070 ORR r0,r0,#0xf00000 +000008 4903 LDR r1,|L2.24| +00000a 6008 STR r0,[r1,#0] +;;;155 #endif +;;;156 +;;;157 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) +;;;158 SystemInit_ExtMemCtl(); +;;;159 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ +;;;160 +;;;161 /* Configure the Vector Table location add offset address ------------------*/ +;;;162 #ifdef VECT_TAB_SRAM +;;;163 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +;;;164 #else +;;;165 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +00000c f04f6000 MOV r0,#0x8000000 +000010 4901 LDR r1,|L2.24| +000012 3980 SUBS r1,r1,#0x80 +000014 6008 STR r0,[r1,#0] +;;;166 #endif +;;;167 } +000016 4770 BX lr +;;;168 + ENDP + + |L2.24| + DCD 0xe000ed88 + + AREA ||.constdata||, DATA, READONLY, ALIGN=0 + + AHBPrescTable +000000 00000000 DCB 0x00,0x00,0x00,0x00 +000004 00000000 DCB 0x00,0x00,0x00,0x00 +000008 01020304 DCB 0x01,0x02,0x03,0x04 +00000c 06070809 DCB 0x06,0x07,0x08,0x09 + APBPrescTable +000010 00000000 DCB 0x00,0x00,0x00,0x00 +000014 01020304 DCB 0x01,0x02,0x03,0x04 + + AREA ||.data||, DATA, ALIGN=2 + + SystemCoreClock + DCD 0x00f42400 + +;*** Start embedded assembler *** + +#line 1 "RTE\\Device\\STM32F401RETx\\system_stm32f4xx.c" + AREA ||.rev16_text||, CODE + THUMB + EXPORT |__asm___18_system_stm32f4xx_c_5d646a67____REV16| +#line 481 "C:\\Users\\User\\AppData\\Local\\Arm\\Packs\\ARM\\CMSIS\\5.7.0\\CMSIS\\Core\\Include\\cmsis_armcc.h" +|__asm___18_system_stm32f4xx_c_5d646a67____REV16| PROC +#line 482 + + rev16 r0, r0 + bx lr + ENDP + AREA ||.revsh_text||, CODE + THUMB + EXPORT |__asm___18_system_stm32f4xx_c_5d646a67____REVSH| +#line 496 +|__asm___18_system_stm32f4xx_c_5d646a67____REVSH| PROC +#line 497 + + revsh r0, r0 + bx lr + ENDP + AREA ||.rrx_text||, CODE + THUMB + EXPORT |__asm___18_system_stm32f4xx_c_5d646a67____RRX| +#line 683 +|__asm___18_system_stm32f4xx_c_5d646a67____RRX| PROC +#line 684 + + rrx r0, r0 + bx lr + ENDP + +;*** End embedded assembler *** diff --git a/workshop-1/RTE/Device/STM32F401RETx/startup_stm32f401xe.s b/workshop-1/RTE/Device/STM32F401RETx/startup_stm32f401xe.s new file mode 100644 index 0000000..8a9e9d2 --- /dev/null +++ b/workshop-1/RTE/Device/STM32F401RETx/startup_stm32f401xe.s @@ -0,0 +1,377 @@ +;******************************************************************************* +;* File Name : startup_stm32f401xe.s +;* Author : MCD Application Team +;* Description : STM32F401xe devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* @attention +;* +;*

© Copyright (c) 2017 STMicroelectronics. +;* All rights reserved.

+;* +;* This software component is licensed by ST under BSD 3-Clause license, +;* the "License"; You may not use this file except in compliance with the +;* License. You may obtain a copy of the License at: +;* opensource.org/licenses/BSD-3-Clause +;* +;******************************************************************************* +;* <<< Use Configuration Wizard in Context Menu >>> +; +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD 0 ; Reserved + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD 0 ; Reserved + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FPU_IRQHandler ; FPU + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI4_IRQHandler ; SPI4 + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +DMA1_Stream7_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +FPU_IRQHandler +SPI4_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/workshop-1/RTE/Device/STM32F401RETx/system_stm32f4xx.c b/workshop-1/RTE/Device/STM32F401RETx/system_stm32f4xx.c new file mode 100644 index 0000000..a9cfc96 --- /dev/null +++ b/workshop-1/RTE/Device/STM32F401RETx/system_stm32f4xx.c @@ -0,0 +1,727 @@ +/** + ****************************************************************************** + * @file system_stm32f4xx.c + * @author MCD Application Team + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f4xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f4xx_system + * @{ + */ + +/** @addtogroup STM32F4xx_System_Private_Includes + * @{ + */ + + +#include "stm32f4xx.h" + +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Defines + * @{ + */ + +/************************* Miscellaneous Configuration ************************/ +/*!< Uncomment the following line if you need to use external SRAM or SDRAM as data memory */ +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\ + || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) +/* #define DATA_IN_ExtSRAM */ +#endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx || STM32F469xx || STM32F479xx ||\ + STM32F412Zx || STM32F412Vx */ + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) +/* #define DATA_IN_ExtSDRAM */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\ + STM32F479xx */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +/******************************************************************************/ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Variables + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +uint32_t SystemCoreClock = 16000000; +const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes + * @{ + */ + +#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the FPU setting, vector table location and External memory + * configuration. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + #endif + +#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value + * depends on the application requirements), user has to ensure that HSE_VALUE + * is same as the real frequency of the crystal used. Otherwise, this function + * may have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +#if defined (DATA_IN_ExtSRAM) && defined (DATA_IN_ExtSDRAM) +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F469xx) || defined(STM32F479xx) +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f4xx.s before jump to main. + * This function configures the external memories (SRAM/SDRAM) + * This SRAM/SDRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ + __IO uint32_t tmp = 0x00; + + register uint32_t tmpreg = 0, timeout = 0xFFFF; + register __IO uint32_t index; + + /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface clock */ + RCC->AHB1ENR |= 0x000001F8; + + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN); + + /* Connect PDx pins to FMC Alternate function */ + GPIOD->AFR[0] = 0x00CCC0CC; + GPIOD->AFR[1] = 0xCCCCCCCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xAAAA0A8A; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xFFFF0FCF; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FMC Alternate function */ + GPIOE->AFR[0] = 0xC00CC0CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA828A; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xFFFFC3CF; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FMC Alternate function */ + GPIOF->AFR[0] = 0xCCCCCCCC; + GPIOF->AFR[1] = 0xCCCCCCCC; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA800AAA; + /* Configure PFx pins speed to 50 MHz */ + GPIOF->OSPEEDR = 0xAA800AAA; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FMC Alternate function */ + GPIOG->AFR[0] = 0xCCCCCCCC; + GPIOG->AFR[1] = 0xCCCCCCCC; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0xAAAAAAAA; + /* Configure PGx pins speed to 50 MHz */ + GPIOG->OSPEEDR = 0xAAAAAAAA; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + + /* Connect PHx pins to FMC Alternate function */ + GPIOH->AFR[0] = 0x00C0CC00; + GPIOH->AFR[1] = 0xCCCCCCCC; + /* Configure PHx pins in Alternate function mode */ + GPIOH->MODER = 0xAAAA08A0; + /* Configure PHx pins speed to 50 MHz */ + GPIOH->OSPEEDR = 0xAAAA08A0; + /* Configure PHx pins Output type to push-pull */ + GPIOH->OTYPER = 0x00000000; + /* No pull-up, pull-down for PHx pins */ + GPIOH->PUPDR = 0x00000000; + + /* Connect PIx pins to FMC Alternate function */ + GPIOI->AFR[0] = 0xCCCCCCCC; + GPIOI->AFR[1] = 0x00000CC0; + /* Configure PIx pins in Alternate function mode */ + GPIOI->MODER = 0x0028AAAA; + /* Configure PIx pins speed to 50 MHz */ + GPIOI->OSPEEDR = 0x0028AAAA; + /* Configure PIx pins Output type to push-pull */ + GPIOI->OTYPER = 0x00000000; + /* No pull-up, pull-down for PIx pins */ + GPIOI->PUPDR = 0x00000000; + +/*-- FMC Configuration -------------------------------------------------------*/ + /* Enable the FMC interface clock */ + RCC->AHB3ENR |= 0x00000001; + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + + FMC_Bank5_6->SDCR[0] = 0x000019E4; + FMC_Bank5_6->SDTR[0] = 0x01115351; + + /* SDRAM initialization sequence */ + /* Clock enable command */ + FMC_Bank5_6->SDCMR = 0x00000011; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Delay */ + for (index = 0; index<1000; index++); + + /* PALL command */ + FMC_Bank5_6->SDCMR = 0x00000012; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Auto refresh command */ + FMC_Bank5_6->SDCMR = 0x00000073; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* MRD register program */ + FMC_Bank5_6->SDCMR = 0x00046014; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Set refresh count */ + tmpreg = FMC_Bank5_6->SDRTR; + FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); + + /* Disable write protection */ + tmpreg = FMC_Bank5_6->SDCR[0]; + FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[2] = 0x00001011; + FMC_Bank1->BTCR[3] = 0x00000201; + FMC_Bank1E->BWTR[2] = 0x0fffffff; +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +#if defined(STM32F469xx) || defined(STM32F479xx) + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[2] = 0x00001091; + FMC_Bank1->BTCR[3] = 0x00110212; + FMC_Bank1E->BWTR[2] = 0x0fffffff; +#endif /* STM32F469xx || STM32F479xx */ + + (void)(tmp); +} +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ +#elif defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f4xx.s before jump to main. + * This function configures the external memories (SRAM/SDRAM) + * This SRAM/SDRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ + __IO uint32_t tmp = 0x00; +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) +#if defined (DATA_IN_ExtSDRAM) + register uint32_t tmpreg = 0, timeout = 0xFFFF; + register __IO uint32_t index; + +#if defined(STM32F446xx) + /* Enable GPIOA, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG interface + clock */ + RCC->AHB1ENR |= 0x0000007D; +#else + /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface + clock */ + RCC->AHB1ENR |= 0x000001F8; +#endif /* STM32F446xx */ + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN); + +#if defined(STM32F446xx) + /* Connect PAx pins to FMC Alternate function */ + GPIOA->AFR[0] |= 0xC0000000; + GPIOA->AFR[1] |= 0x00000000; + /* Configure PDx pins in Alternate function mode */ + GPIOA->MODER |= 0x00008000; + /* Configure PDx pins speed to 50 MHz */ + GPIOA->OSPEEDR |= 0x00008000; + /* Configure PDx pins Output type to push-pull */ + GPIOA->OTYPER |= 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOA->PUPDR |= 0x00000000; + + /* Connect PCx pins to FMC Alternate function */ + GPIOC->AFR[0] |= 0x00CC0000; + GPIOC->AFR[1] |= 0x00000000; + /* Configure PDx pins in Alternate function mode */ + GPIOC->MODER |= 0x00000A00; + /* Configure PDx pins speed to 50 MHz */ + GPIOC->OSPEEDR |= 0x00000A00; + /* Configure PDx pins Output type to push-pull */ + GPIOC->OTYPER |= 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOC->PUPDR |= 0x00000000; +#endif /* STM32F446xx */ + + /* Connect PDx pins to FMC Alternate function */ + GPIOD->AFR[0] = 0x000000CC; + GPIOD->AFR[1] = 0xCC000CCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xA02A000A; + /* Configure PDx pins speed to 50 MHz */ + GPIOD->OSPEEDR = 0xA02A000A; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FMC Alternate function */ + GPIOE->AFR[0] = 0xC00000CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA800A; + /* Configure PEx pins speed to 50 MHz */ + GPIOE->OSPEEDR = 0xAAAA800A; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FMC Alternate function */ + GPIOF->AFR[0] = 0xCCCCCCCC; + GPIOF->AFR[1] = 0xCCCCCCCC; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA800AAA; + /* Configure PFx pins speed to 50 MHz */ + GPIOF->OSPEEDR = 0xAA800AAA; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FMC Alternate function */ + GPIOG->AFR[0] = 0xCCCCCCCC; + GPIOG->AFR[1] = 0xCCCCCCCC; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0xAAAAAAAA; + /* Configure PGx pins speed to 50 MHz */ + GPIOG->OSPEEDR = 0xAAAAAAAA; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F469xx) || defined(STM32F479xx) + /* Connect PHx pins to FMC Alternate function */ + GPIOH->AFR[0] = 0x00C0CC00; + GPIOH->AFR[1] = 0xCCCCCCCC; + /* Configure PHx pins in Alternate function mode */ + GPIOH->MODER = 0xAAAA08A0; + /* Configure PHx pins speed to 50 MHz */ + GPIOH->OSPEEDR = 0xAAAA08A0; + /* Configure PHx pins Output type to push-pull */ + GPIOH->OTYPER = 0x00000000; + /* No pull-up, pull-down for PHx pins */ + GPIOH->PUPDR = 0x00000000; + + /* Connect PIx pins to FMC Alternate function */ + GPIOI->AFR[0] = 0xCCCCCCCC; + GPIOI->AFR[1] = 0x00000CC0; + /* Configure PIx pins in Alternate function mode */ + GPIOI->MODER = 0x0028AAAA; + /* Configure PIx pins speed to 50 MHz */ + GPIOI->OSPEEDR = 0x0028AAAA; + /* Configure PIx pins Output type to push-pull */ + GPIOI->OTYPER = 0x00000000; + /* No pull-up, pull-down for PIx pins */ + GPIOI->PUPDR = 0x00000000; +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ + +/*-- FMC Configuration -------------------------------------------------------*/ + /* Enable the FMC interface clock */ + RCC->AHB3ENR |= 0x00000001; + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + + /* Configure and enable SDRAM bank1 */ +#if defined(STM32F446xx) + FMC_Bank5_6->SDCR[0] = 0x00001954; +#else + FMC_Bank5_6->SDCR[0] = 0x000019E4; +#endif /* STM32F446xx */ + FMC_Bank5_6->SDTR[0] = 0x01115351; + + /* SDRAM initialization sequence */ + /* Clock enable command */ + FMC_Bank5_6->SDCMR = 0x00000011; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Delay */ + for (index = 0; index<1000; index++); + + /* PALL command */ + FMC_Bank5_6->SDCMR = 0x00000012; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Auto refresh command */ +#if defined(STM32F446xx) + FMC_Bank5_6->SDCMR = 0x000000F3; +#else + FMC_Bank5_6->SDCMR = 0x00000073; +#endif /* STM32F446xx */ + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* MRD register program */ +#if defined(STM32F446xx) + FMC_Bank5_6->SDCMR = 0x00044014; +#else + FMC_Bank5_6->SDCMR = 0x00046014; +#endif /* STM32F446xx */ + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Set refresh count */ + tmpreg = FMC_Bank5_6->SDRTR; +#if defined(STM32F446xx) + FMC_Bank5_6->SDRTR = (tmpreg | (0x0000050C<<1)); +#else + FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); +#endif /* STM32F446xx */ + + /* Disable write protection */ + tmpreg = FMC_Bank5_6->SDCR[0]; + FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); +#endif /* DATA_IN_ExtSDRAM */ +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ + +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)\ + || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)\ + || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) + +#if defined(DATA_IN_ExtSRAM) +/*-- GPIOs Configuration -----------------------------------------------------*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR |= 0x00000078; + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN); + + /* Connect PDx pins to FMC Alternate function */ + GPIOD->AFR[0] = 0x00CCC0CC; + GPIOD->AFR[1] = 0xCCCCCCCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xAAAA0A8A; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xFFFF0FCF; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FMC Alternate function */ + GPIOE->AFR[0] = 0xC00CC0CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA828A; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xFFFFC3CF; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FMC Alternate function */ + GPIOF->AFR[0] = 0x00CCCCCC; + GPIOF->AFR[1] = 0xCCCC0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA000AAA; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xFF000FFF; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FMC Alternate function */ + GPIOG->AFR[0] = 0x00CCCCCC; + GPIOG->AFR[1] = 0x000000C0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00085AAA; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000CAFFF; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*-- FMC/FSMC Configuration --------------------------------------------------*/ + /* Enable the FMC/FSMC interface clock */ + RCC->AHB3ENR |= 0x00000001; + +#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[2] = 0x00001011; + FMC_Bank1->BTCR[3] = 0x00000201; + FMC_Bank1E->BWTR[2] = 0x0fffffff; +#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +#if defined(STM32F469xx) || defined(STM32F479xx) + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[2] = 0x00001091; + FMC_Bank1->BTCR[3] = 0x00110212; + FMC_Bank1E->BWTR[2] = 0x0fffffff; +#endif /* STM32F469xx || STM32F479xx */ +#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)\ + || defined(STM32F412Zx) || defined(STM32F412Vx) + /* Delay after an RCC peripheral clock enabling */ + tmp = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN); + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001011; + FSMC_Bank1->BTCR[3] = 0x00000201; + FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF; +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx */ + +#endif /* DATA_IN_ExtSRAM */ +#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\ + STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx */ + (void)(tmp); +} +#endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/workshop-1/RTE/_Target_1/RTE_Components.h b/workshop-1/RTE/_Target_1/RTE_Components.h new file mode 100644 index 0000000..c752ae1 --- /dev/null +++ b/workshop-1/RTE/_Target_1/RTE_Components.h @@ -0,0 +1,32 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'hash' + * Target: 'Target 1' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "stm32f4xx.h" + +/* Keil.ARM Compiler::Compiler:I/O:STDERR:ITM:1.2.0 */ +#define RTE_Compiler_IO_STDERR /* Compiler I/O: STDERR */ + #define RTE_Compiler_IO_STDERR_ITM /* Compiler I/O: STDERR ITM */ +/* Keil.ARM Compiler::Compiler:I/O:STDIN:ITM:1.2.0 */ +#define RTE_Compiler_IO_STDIN /* Compiler I/O: STDIN */ + #define RTE_Compiler_IO_STDIN_ITM /* Compiler I/O: STDIN ITM */ +/* Keil.ARM Compiler::Compiler:I/O:STDOUT:ITM:1.2.0 */ +#define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */ + #define RTE_Compiler_IO_STDOUT_ITM /* Compiler I/O: STDOUT ITM */ +/* Keil::Device:Startup:2.6.3 */ +#define RTE_DEVICE_STARTUP_STM32F4XX /* Device Startup for STM32F4 */ + + +#endif /* RTE_COMPONENTS_H */ diff --git a/workshop-1/hash.uvprojx b/workshop-1/hash.uvprojx new file mode 100644 index 0000000..53fb0e1 --- /dev/null +++ b/workshop-1/hash.uvprojx @@ -0,0 +1,466 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 5060960::V5.06 update 7 (build 960)::.\ARMCC + 0 + + + STM32F401RETx + STMicroelectronics + Keil.STM32F4xx_DFP.2.15.0 + http://www.keil.com/pack/ + IRAM(0x20000000,0x00018000) IROM(0x08000000,0x00080000) CPUTYPE("Cortex-M4") FPU2 CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F4xx_512 -FS08000000 -FL080000 -FP0($$Device:STM32F401RETx$CMSIS\Flash\STM32F4xx_512.FLM)) + 0 + $$Device:STM32F401RETx$Drivers\CMSIS\Device\ST\STM32F4xx\Include\stm32f4xx.h + + + + + + + + + + $$Device:STM32F401RETx$CMSIS\SVD\STM32F401xE.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + hash + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x18000 + + + 1 + 0x8000000 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0x18000 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 3 + 3 + 1 + 1 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + + + + + + + + + Source Group 1 + + + hash_function.c + 1 + .\hash_function.c + + + hash_lookup_table.s + 2 + .\hash_lookup_table.s + + + + + ::CMSIS + + + ::Compiler + + + ::Device + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + RTE\Device\STM32F401RETx\startup_stm32f401xe.s + + + + + + + + RTE\Device\STM32F401RETx\system_stm32f4xx.c + + + + + + + + + + diff --git a/workshop-1/hash_function.c b/workshop-1/hash_function.c new file mode 100644 index 0000000..e52cd38 --- /dev/null +++ b/workshop-1/hash_function.c @@ -0,0 +1,55 @@ +#include +#include + +static const uint8_t hashtbl[] = { + 18, 11, 10, 21, 7, 5, 9, 22, 17, 2, 12, 3, 19, 1, 14, 16, 20, 8, 23, 4, 26, 15, 6, 24, 13, 25 +}; + +__asm int generate_hash( const char *str, const uint8_t *hashtbl ) +{ + // Define names for used registers +input_str RN r0 +hashtbl RN r1 +curr_char RN r2 +hash_val RN r3 + + MOV hash_val, #0 // Initialize hash_val to zero +hash_loop + LDRB curr_char, [input_str] // Load byte into curr_char from memory pointed to by input_str + CMP curr_char, #'0' // Compare it with 0 + BLS hash_skip // If it is lower or same in the ASCII table, then skip this character + + CMP curr_char, #'9' // Compare it with 9 + SUBLS hash_val, curr_char // If byte is lower or same, then subtract its value from the hash_val + ADDLS hash_val, #48 // Add 48 to the hash_val because ASCII '0' index is 48 decimal + BLS hash_skip // Then move the the next character + + CMP curr_char, #'A' - 1 // Compare it with the character before 'A' + BLS hash_skip // If it is lower or same in the ASCII table, then skip this character + + CMP curr_char, #'Z' // Compare it with the 'Z' character + BHI hash_skip // If it is higher in the ASCII table, then skip this character + + SUB r4, curr_char, #65 // Subtract 65 from curr_char because the ASCII 'A' index is 65 decimal and store in r4 + ADD r4, hashtbl, r4 // Add the address of the start of the lookup table to r4 + LDRB r5, [r4] // Load byte into r5 from memory pointed to by r4 (character hash value) + ADD hash_val, r5 // Add the character hash value to the hash_val + +hash_skip + ADDS input_str, input_str, #1 // Increment the input_str pointer + CMP curr_char, #0 // Check if the byte is 0 + BNE hash_loop // If not, repeat loop + MOVEQ r0, hash_val // Else store hash_val to r0 + BX lr // Return from subroutine +} + +int main(void) +{ + static char STRING_TO_HASH[] = "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789!!@#$%*&"; + int hash = 0; + + hash = generate_hash(STRING_TO_HASH, hashtbl); + printf("%d", hash); + + return 0; +}