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266 lines
11 KiB
266 lines
11 KiB
5 years ago
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;- ----------------------------------------------------------------------------
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;- ATMEL Microcontroller Software Support - ROUSSET -
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;- ----------------------------------------------------------------------------
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;- DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
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;- IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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;- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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;- DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
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;- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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;- LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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;- OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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;- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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;- NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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;- EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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;- ----------------------------------------------------------------------------
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;- File source : Cstartup.s79
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;- Object : Generic CStartup
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;- 1.0 01/Sep/05 FBr : Creation
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;- 1.1 09/Sep/05 JPP : Change Interrupt management
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;------------------------------------------------------------------------------
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;------------------------------------------------------------------------------
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; Include your AT91 Library files
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;------------------------------------------------------------------------------
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#include "AT91SAM7X256_inc.h"
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;------------------------------------------------------------------------------
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;------------------------------------------------------------------------------
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; ?RESET
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; Reset Vector.
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; Normally, segment INTVEC is linked at address 0.
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; For debugging purposes, INTVEC may be placed at other addresses.
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; A debugger that honors the entry point will start the
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; program in a normal way even if INTVEC is not at address 0.
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;------------------------------------------------------------------------------
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PROGRAM ?RESET ;- Begins a program module
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RSEG INTRAMEND_REMAP ;- Begins a relocatable segment
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RSEG ICODE:CODE (2) ;- Begins a relocatable segment : corresponding address is 32-bit aligned
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CODE32 ;- Always ARM mode after reset
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ORG 0 ;- Sets the location counter: corresponds to the RESET vector address
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;------------------------------------------------------------------------------
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;- Exception vectors
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;------------------------------------------------------------------------------
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;- These vectors can be read at address 0 or at RAM address
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;- They ABSOLUTELY requires to be in relative addresssing mode in order to
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;- guarantee a valid jump. For the moment, all are just looping.
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;- If an exception occurs before remap, this would result in an infinite loop.
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;- To ensure if a exeption occurs before start application to infinite loop.
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;------------------------------------------------------------------------------
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reset
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B InitReset ; 0x00 Reset handler
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undefvec:
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B undefvec ; 0x04 Undefined Instruction
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swivec:
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B swivec ; 0x08 Software Interrupt
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pabtvec:
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B pabtvec ; 0x0C Prefetch Abort
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dabtvec:
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B dabtvec ; 0x10 Data Abort
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rsvdvec:
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B rsvdvec ; 0x14 reserved
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irqvec:
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B IRQ_Handler_Entry ; 0x18 IRQ
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fiqvec: ; 0x1c FIQ
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;------------------------------------------------------------------------------
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;- Function : FIQ_Handler_Entry
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;- Treatments : FIQ Controller Interrupt Handler.
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;- Called Functions : AIC_FVR[interrupt]
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;------------------------------------------------------------------------------
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FIQ_Handler_Entry:
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;- Switch in SVC/User Mode to allow User Stack access for C code
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; because the FIQ is not yet acknowledged
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;- Save and r0 in FIQ_Register
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mov r9,r0
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ldr r0 , [r8, #AIC_FVR]
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msr CPSR_c,#I_BIT | F_BIT | ARM_MODE_SVC
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;- Save scratch/used registers and LR in User Stack
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stmfd sp!, { r1-r3, r12, lr}
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;- Branch to the routine pointed by the AIC_FVR
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mov r14, pc
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bx r0
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;- Restore scratch/used registers and LR from User Stack
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ldmia sp!, { r1-r3, r12, lr}
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;- Leave Interrupts disabled and switch back in FIQ mode
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msr CPSR_c, #I_BIT | F_BIT | ARM_MODE_FIQ
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;- Restore the R0 ARM_MODE_SVC register
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mov r0,r9
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;- Restore the Program Counter using the LR_fiq directly in the PC
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subs pc,lr,#4
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;------------------------------------------------------------------------------
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;- Manage exception: The exception must be ensure in ARM mode
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;------------------------------------------------------------------------------
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;------------------------------------------------------------------------------
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;- Function : IRQ_Handler_Entry
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;- Treatments : IRQ Controller Interrupt Handler.
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;- Called Functions : AIC_IVR[interrupt]
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;------------------------------------------------------------------------------
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IRQ_Handler_Entry:
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;-------------------------
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;- Manage Exception Entry
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;-------------------------
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;- Adjust and save LR_irq in IRQ stack
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sub lr, lr, #4
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stmfd sp!, {lr}
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;- Save r0 and SPSR (need to be saved for nested interrupt)
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mrs r14, SPSR
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stmfd sp!, {r0,r14}
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;- Write in the IVR to support Protect Mode
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;- No effect in Normal Mode
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;- De-assert the NIRQ and clear the source in Protect Mode
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ldr r14, =AT91C_BASE_AIC
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ldr r0 , [r14, #AIC_IVR]
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str r14, [r14, #AIC_IVR]
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;- Enable Interrupt and Switch in Supervisor Mode
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msr CPSR_c, #ARM_MODE_SVC
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;- Save scratch/used registers and LR in User Stack
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stmfd sp!, { r1-r3, r12, r14}
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;----------------------------------------------
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;- Branch to the routine pointed by the AIC_IVR
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;----------------------------------------------
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mov r14, pc
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bx r0
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;----------------------------------------------
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;- Manage Exception Exit
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;----------------------------------------------
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;- Restore scratch/used registers and LR from User Stack
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ldmia sp!, { r1-r3, r12, r14}
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;- Disable Interrupt and switch back in IRQ mode
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msr CPSR_c, #I_BIT | ARM_MODE_IRQ
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;- Mark the End of Interrupt on the AIC
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ldr r14, =AT91C_BASE_AIC
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str r14, [r14, #AIC_EOICR]
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;- Restore SPSR_irq and r0 from IRQ stack
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ldmia sp!, {r0,r14}
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msr SPSR_cxsf, r14
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;- Restore adjusted LR_irq from IRQ stack directly in the PC
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ldmia sp!, {pc}^
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InitReset:
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;------------------------------------------------------------------------------
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;- Low level Init is performed in a C function: AT91F_LowLevelInit
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;- Init Stack Pointer to a valid memory area before calling AT91F_LowLevelInit
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;------------------------------------------------------------------------------
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;- Retrieve end of RAM address
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__iramend EQU SFB(INTRAMEND_REMAP) ;- Segment begin
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EXTERN AT91F_LowLevelInit
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ldr r13,=__iramend ;- Temporary stack in internal RAM for Low Level Init execution
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ldr r0,=AT91F_LowLevelInit
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mov lr, pc
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bx r0 ;- Branch on C function (with interworking)
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;------------------------------------------------------------------------------
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;- Top of Stack Definition
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;------------------------------------------------------------------------------
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;- Interrupt and Supervisor Stack are located at the top of internal memory in
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;- order to speed the exception handling context saving and restoring.
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;- ARM_MODE_SVC (Application, C) Stack is located at the top of the external memory.
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;------------------------------------------------------------------------------
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IRQ_STACK_SIZE EQU (3*8*4) ; 3 words to be saved per interrupt priority level
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ARM_MODE_FIQ EQU 0x11
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ARM_MODE_IRQ EQU 0x12
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ARM_MODE_SVC EQU 0x13
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I_BIT EQU 0x80
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F_BIT EQU 0x40
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;------------------------------------------------------------------------------
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;- Setup the stack for each mode
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;------------------------------------------------------------------------------
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ldr r0, =__iramend
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;- Set up Fast Interrupt Mode and set FIQ Mode Stack
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msr CPSR_c, #ARM_MODE_FIQ | I_BIT | F_BIT
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;- Init the FIQ register
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ldr r8, =AT91C_BASE_AIC
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;- Set up Interrupt Mode and set IRQ Mode Stack
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msr CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT
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mov r13, r0 ; Init stack IRQ
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sub r0, r0, #IRQ_STACK_SIZE
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;- Enable interrupt & Set up Supervisor Mode and set Supervisor Mode Stack
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msr CPSR_c, #ARM_MODE_SVC
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mov r13, r0
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;------------------------------------------------------------------------------
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; Initialize segments.
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;------------------------------------------------------------------------------
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; __segment_init is assumed to use
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; instruction set and to be reachable by BL from the ICODE segment
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; (it is safest to link them in segment ICODE).
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;------------------------------------------------------------------------------
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EXTERN __segment_init
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ldr r0,=__segment_init
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mov lr, pc
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bx r0
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;------------------------------------------------------------------------------
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;- Branch on C code Main function (with interworking)
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;------------------------------------------------------------------------------
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EXTERN main
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PUBLIC __main
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?jump_to_main:
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ldr lr,=?call_exit
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ldr r0,=main
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__main:
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bx r0
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;------------------------------------------------------------------------------
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;- Loop for ever
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;------------------------------------------------------------------------------
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;- End of application. Normally, never occur.
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;- Could jump on Software Reset ( B 0x0 ).
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;------------------------------------------------------------------------------
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?call_exit:
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End
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b End
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;------------------------------------------------------------------------------
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;- Exception Vectors
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;------------------------------------------------------------------------------
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PUBLIC AT91F_Default_FIQ_handler
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PUBLIC AT91F_Default_IRQ_handler
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PUBLIC AT91F_Spurious_handler
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CODE32 ; Always ARM mode after exeption
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AT91F_Default_FIQ_handler
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b AT91F_Default_FIQ_handler
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AT91F_Default_IRQ_handler
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b AT91F_Default_IRQ_handler
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AT91F_Spurious_handler
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b AT91F_Spurious_handler
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ENDMOD ;- Terminates the assembly of the current module
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END ;- Terminates the assembly of the last module in a file
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